A recognition that transistors of different types have different operating characteristics based on the nature of the crystalline structure has resulted in the development of semiconductor structures that are selected based on the transistor type. For example, N channel transistors have higher carrier mobility when formed in silicon with a (100) surface orientation than in a (110) surface orientation. The opposite is true for P channel transistors. Thus, techniques have been developed for forming the N channel transistors in a (100) surface orientation and P channel transistors in a (110) surface orientation. Similarly, techniques have been developed for forming N channel transistors in silicon that is under tensile stress and P channel transistors that are under compressive stress along the direction of the current flow in a <110> crystal direction. One of the difficulties in achieving these results has been achieving the particular enhancing property for both transistor types on the same integrated circuit. The complexity is further increased when semiconductor-on-insulator (SOI) is the desired technique for both transistor types.
Thus, there is a need for a method for overcoming or at least reducing the difficulties in achieving different semiconductor properties for the transistor types for enhancing performance.